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| ISD5008 Single-Chip Voice Record/Playback Device 4-, 5-, 6-, and 8-Minute Durations Preliminary Datasheet ISD5008 PRODUCT SUMMARY The ISD5008 ChipCorder product is a fully-integrated, single-chip solution which provides seamless integration of enhanced voice record and playback features for digital cellular phones (GSM, CDMA, TDMA, PDC, and PHS), automotive communications, GPS/navigation systems, and portable communication products. This low-power, 3volt product enables customers to quickly and easily integrate 4 to 8 minutes of voice storage features such as one-way and two-way (full duplex) call record, voice memo record, and call screening/answering machine functionality. Like other ChipCorder products, the ISD5008 integrates the sampling clock, anti-aliasing and smoothing filters, and the multi-level storage array on a single-chip. For enhanced voice features, the ISD5008 eliminates external circuitry by also integrating automatic gain control (AGC), a power amplifier/speaker driver, volume control, summing amplifiers, analog switches, and a car kit interface. Input level adjustable amplifiers are also included, providing a flexible interface for multiple applications. Figure: ISD5008 Block Diagram FTHRU 6dB INP FILTO CHIP SET ANA OUT AMP 1 ANA OUT MUX ANA OUT+ ANA OUT- MICROPHONE MIC+ MIC AGCCAP AUX IN 1.0/1.414/2.0/2.828 MIC IN INP SUM1 MUX AGC (AGPD) 1 2 SUM1 Summing AMP SUM1 ARRAY 1 SUM1 Input Source MUX Low Pass Filter 1 FILTO ANA IN 2 SUM2 Summing AMP VOL SUM2 Filter MUX MUX (AOPD) 3 FILTO ANA IN ARRAY ( S1M0 ) S1M1 (FLS0) (FLPD) CAR KIT AUX IN ( S2M0 ) S2M1 Multilevel Storage Array FILTO AUX IN AMP (INS0) 1 1 () AOS0 AOS1 AOS2 SUM1 MUX (AXPD) 2 ( AXG0) AXG1 2 Internal Clock 2 CAR KIT AUX OUT AMP ( S1S0 ) S1S1 XCLK 0.625/0.883/1.25/1.76 ( FLD0 FLD1 ) AUX OUT Output MUX VOL SUM2 SPEAKER Spkr. AMP CHIP SET ANA IN SP+ SP- ANA IN AMP (AIPD) 1 ANA IN 2 SUM1 INP ANA IN SUM2 Volume Control 3 ( OPS0 ) OPS1 1 2 Vol MUX ( OPA0 OPA1 ) 2 ( AIG0 ) AIG1 Power Conditioning 2 () VOL0 VOL1 VOL2 (VLPD) ( VLS0 ) VLS1 Device Control VCCA VSSA VSSA VSSA VSSD VSSD VCCD VCCD SCLK SS MOSI MISO INT RAC August 2000 ISD * 2727 North First Street, San Jose, CA 95134 * TEL: 408/943-6666 * FAX: 408/544-1787 * http://www.isd.com ISD5008 Product Duration/sample rate selection is accomplished via software, allowing customers to optimize quality and duration for various features within the same end product. The ISD5008 device is designed for use in a microprocessor- or microcontroller-based system. Address, control, and duration selection are accomplished through a Serial Peripheral Interface (SPI) or Microwire Serial Interface to minimize pin count. Recordings are stored in on-chip nonvolatile memory cells, providing zero-power message storage. This unique, single-chip solution is made possible through ISD's patented multilevel storage technology. Voice and audio signals are stored directly into solid-state memory in their natural, uncompressed form, providing superior quality voice and music reproduction. ENHANCED VOICE FEATURES * * * * * * * One or two-way (full duplex) conversation record (record signal summation) One- or two-way (full duplex) message playback (while on a call) Voice memo record and playback Private call screening In-terminal answering machine Personalized outgoing message (given caller ID information from host chip set) Private call announce while on call (given CIDCW information from host chip set) EASY-TO-USE AND CONTROL * * No compression algorithm development required User-controllable sample rates of 8.0 kHz, 6.4 kHz, 5.3 kHz, or 4.0 kHz providing up to 8 minutes of voice storage. Microcontroller SPI or MicrowireTM Serial Interface Fully addressable to handle multiple messages in 1200 rows ISD5008 FEATURES FULLY-INTEGRATED SOLUTION * * * Single-chip voice record/playback solution Integrated sampling clock, anti-aliasing and smoothing filters, and multi-level storage array Integrated analog features such as automatic gain control (AGC), audio gating switches, speaker driver (23mW with 8 ohm load), summing amplifiers, volume control, and an AUX IN/AUX OUT interface (e.g., for car kits). * * HIGH QUALITY SOLUTION * * * High quality voice and music reproduction ISD's standard 100-year message retention (typical) 100,000 record cycles (typical) LOW-POWER CONSUMPTION * * Single +3 volt supply Operating current: ICC Play = 15 mA (typical) ICC Rec = 25 mA (typical) ICC Feedthru = 12 mA (typical) Standby current: ISB = 1 A OPTIONS * * Available in die form, PDIP, SOIC, TSOP, and chip scale packaging (CSP) Compact BGA chip scale package available for portable applications Extended temperature (-20 to +70C) and industrial temperature (-40 to +85C) versions available * * * * Power consumption controlled by SPI or Microwire control register Most stages can be individually powered down for minimum power consumption ii Voice Solutions in SiliconTM Table of Contents 1 DETAILED DESCRIPTION ................................................. .................... 1 1.1 Speech/Sound Quality ...................................... .................... 1 1.2 Duration ............................................................ .................... 1 1.3 Flash Storage .................................................... .................... 1 1.4 Microcontroller Interface ....................................................... 1 1.5 Programming .................................................... .................... 1 PIN DESCRIPTIONS ........................................................ .................... 2 2.1 Digital I/O Pins ................................................... .................... 2 2.2 Analog I/O Pins .................................................. .................... 3 2.3 Power and Ground Pins .................................... .................... 6 INTERNAL FUNCTIONAL BLOCKS .................................... .................... 7 SERIAL PERIPHERAL INTERFACE (SPI) DESCRIPTION .......... .................... 13 4.1 Message Cueing .............................................. .................... 13 4.2 Power-Up Sequence ......................................... .................... 14 4.3 SPI Port .............................................................. .................... 15 4.4 SPI Control Register ........................................... .................... 15 OPERATIONAL MODES DESCRIPTION ............................. .................... 21 5.1 Feed Through Mode ......................................... .................... 21 5.2 Call Record ...................................................... .................... 23 5.3 Memo Record .................................................. .................... 24 5.4 Memo and Call Record Playback .................... .................... 24 TIMING DIAGRAMS ....................................................... .................... 34 DEVICE PHYSICAL DIMENSIONS ..................................... .................... 36 ORDERING INFORMATION ........................................... .................... 42 2 3 4 5 6 7 8 ISD5008 Product 1 1.1 DETAILED DESCRIPTION SPEECH/SOUND QUALITY 1.3 FLASH STORAGE The ISD5008 ChipCorder product can be configured via software to operate at 4.0, 5.3, 6.4, and 8.0 kHz sampling frequencies, allowing the user a choice of speech quality options. Increasing the duration decreases the sampling frequency and bandwidth, which affects sound quality. Table 1 compares filter pass band and product durations. The speech samples are stored directly into on-chip nonvolatile memory without the digitization and compression associated with other solutions. Direct analog storage provides a natural sounding reproduction of voice, music, tones, and sound effects not available with most solid-state solutions. One of the benefits of ISD's ChipCorder technology is the use of on-chip nonvolatile memory, which provides zero-power message storage. The message is retained for up to 100 years (typically) without power. In addition, the device can be re-recorded over 100,000 times (typically). 1.4 MICROCONTROLLER INTERFACE 1.2 DURATION A four-wire (SCLK, MOSI, MISO, SS) SPI interface is provided for ISD5008 control, addressing functions, and sample rate selection. The ISD5008 is configured to operate as a peripheral slave device with a microcontroller-based SPI bus interface. Read/Write access to all the internal registers occurs through this SPI interface. An interrupt signal (INT) and internal read-only Status Register are provided for handshake purposes. To meet end system requirements, the ISD5008 device is a single-chip solution which provides from 4 to 8 minutes of voice record and playback, depending on the sample rates defined by customer software. 1.5 PROGRAMMING Table 1: Input Sample Rate (kHz) 8.0 6.4 5.3 4.0 Input Sample Rate to Duration Duration Typical Filter Pass Band (Minutes) (kHz) 4.0 5.0 6.0 8.0 3.4 2.7 2.3 1.7 The ISD5008 series is also ideal for playback-only applications, where single or multiple message Playback is controlled through the SPI port. Once the desired message configuration is created, duplicates can easily be generated via an ISD or third-party programmers. For more information on available application tools and programmers please see the ISD web site at www.isd.com. ISD 1 ISD5008 Product 2 2.1 SCLK PIN DESCRIPTIONS DIGITAL I/O PINS (Serial Clock) OVF Flag. The overflow flag indicates that the end of the ISD5008's analog memory has been reached during a record or playback operation. EOM Flag. The end of message flag is set only during playback, when an EOM is found. There are eight possible EOM markers per row. The SCLK is the clock input to the ISD5008. Generated by the master microcontroller, the SCLK synchronizes data transfers in and out of the device through the MISO and MOSI lines. Data is latched into the ISD5008 on the rising edge of SCLK and shifted out on the falling edge. RAC (Row Address Clock) SS (Slave Select) RAC is an open drain output pin that marks the end of a row. At the 8 kHz sample frequency, the duration of this period is 200 ms. There are 1,200 rows of memory in the ISD5008 devices. RAC stays HIGH for 175 ms and stays LOW for the remaining 25 ms before it reaches the end of the row. The RAC pin remains HIGH for 109.38 sec and stays LOW for 15.63 sec under the Message Cueing mode. See Table 15 Timing Parameters for RAC timing information at other sample rates. When a record command is first initiated, the RAC pin remains HIGH for an extra TRACLO period, to load sample and hold circuits internal to the device. The RAC pin can be used for message management techniques. This input, when LOW, will select the ISD5008 device. MOSI (Master Out Slave In) MOSI is the serial data input to the ISD5008 device. The master microcontroller places data to be clocked into the ISD5008 device on the MOSI line one-half cycle before the rising edge of SCLK. Data is clocked into the device LSB (Least Significant Bit) first. XCLK MISO (Master In Slave Out) MISO is the serial data output of the ISD5008 device. Data is clocked out on the falling edge of SCLK. This output goes into a high-impedance state when the device is not selected. Data is clocked out of the device LSB first. (External Clock Input) The external clock input for the ISD5008 product has an internal pull-down device. Normally, the ISD5008 is operated at one of four internal rates selected for its internal oscillator by the Sample Rate Select bits. If greater precision is required, the device can be clocked through the XCLK pin as described in Table 2. Because the antialiasing and smoothing filters track the Sample Rate Select bits, one must, for optimum performance, change the external clock AND the Sample Rate Configuration bits to one of the four values to properly set the filters to the correct cutoff frequency as described in Table 3. The duty cycle on the input clock is not critical, as the clock is immediately divided by two internally. If the XCLK is not used, this input should be connected to VSSD. INT (Interrupt) INT is an open drain output pin. The ISD5008 interrupt pin goes LOW and stays LOW when an Overflow (OVF) or End of Message (EOM) marker is detected. Each operation that ends in an EOM or OVF generates an interrupt, including the message cueing cycles. The interrupt is cleared the next time an SPI cycle is completed. The interrupt status can be read by a RINT instruction that will give one of the two flags out the MISO line. 2 Voice Solutions in SiliconTM ISD5008 Product Table 2: Duration (Minutes) 4 5 6 8 External Clock Input Table Sample Rate (kHz) 8.0 6.4 5.3 4.0 Required Clock (kHz) 1024 819.2 682.7 512 2.2 ANALOG I/O PINS (Microphone Input+/-) MIC+, MIC - Table 3: FLD1 0 0 1 1 Internal Clock Rate/Filter Edge FLD0 0 1 0 1 Sample Rate (kHz) 8 6.4 5.3 4 Filter Pass Band (kHz) 3.4 2.7 2.3 1.7 The microphone input transfers the voice signal to the on-chip AGC preamplifier or directly to the ANA OUT MUX, depending on the selected path. The direct path to the ANA OUT MUX has a gain of 6 dB so a 208 mVp-p signal across the differential microphone inputs would give 416 mVp-p across the ANA OUT pins. The AGC circuit has a range of 45 dB in order to deliver a nominal 694 mVp-p into the storage array from a typical electret microphone output of 2 to 20 mVp-p. The input impedance is typically 10 k. Figure 1: Microphone Input VCC 1.5 k 220 F 1.5 k MIC+ Internal to the device CCOUP = 0.1 F Electret Microphone WM-54B Panasonic Ra = 10 k 0.1 F 10 k 1.5 k MIC 1 NOTE: fCUTOFF= 2 R C a COUP ISD 3 ISD5008 Product ANA IN (Analog Input) The ANA IN pin is the analog input from the telephone chip set. It can be switched (by the SPI bus) to the speaker output, the array input or to various other paths. This pin is designed to accept a nominal 1.11 Vp-p when at its minimum gain (6 dB) setting. There is additional gain available in 3 dB steps controlled from the SPI bus, if required, up to 15 dB. Figure 2: ANA IN Input Modes Gain Setting 00 01 10 11 Resistor Ratio (Rb/Ra) 63.9/102 77.9/88.1 92.3/73.8 106/60 Gain 0.625 0.88 1.25 1.77 Gain2 (dB) -4.1 -1.1 1.9 4.9 Table 4: ANA IN Amplifier Gain Settings Setting(1) 0TLP Input VPP(3) 1.11 .785 .555 .393 CFG0 Gain(2) AIG1 0 0 1 1 AIG0 0 1 0 1 .625 .883 1.250 1.767 Array In/Out VPP .694 .694 .694 .694 Speaker Out VPP(4) 2.22 2.22 2.22 2.22 6 dB 9 dB 12 dB 15 dB 1. 2. 3. 4. Gain from ANA IN to SP+/- Gain from ANA IN to ARRAY IN 0TLP Input is the reference Transmission Level Point that is used for testing. This level is typically 3 dB below clipping. Speaker Out gain set to 1.6 (High). (Differential) 4 Voice Solutions in SiliconTM ISD5008 Product AUX IN (Auxiliary Input) The AUX IN is an additional audio input to the ISD5008, such as from the microphone circuit in a mobile phone "car kit." This input has a nominal 700 mVp-p level at its minimum gain setting (0 dB). See Table 5. Additional gain is available in 3 dB steps (controlled by the SPI bus) up to 9 dB. Figure 3: AUX IN Input Modes Gain Setting 00 01 10 11 Resistor Ratio (Rb/Ra) 40.1/40.1 47.0/33.2 53.5/26.7 59.2/21 Gain 1.0 1.414 2.0 2.82 Gain (dB) 0 3 6 9 Table 5: AUXIN Amplifier Gain Settings Setting(1) 0TLP Input VPP(3) .694 .491 .347 .245 CFG0 Gain(2) AXG1 0 0 1 1 AXG0 0 1 0 1 1.00 1.41 2.00 2.82 Array In/Out Ana Out VPP(4) VPP .694 .694 .694 .694 .694 .694 .694 .694 0 dB 3 dB 6 dB 9 dB 1. 2. 3. 4. Gain from AUX IN to ANA OUT Gain from AUX IN to ARRAY IN 0TLP Input is the reference Transmission Level Point that is used for testing. This level is typically 3 dB below clipping. Differential ISD 5 ISD5008 Product ANAOUT+/- (Analog Outputs) 2.3 POWER AND GROUND PINS This differential output is designed to go to the microphone input of the telephone chip set. It is designed to drive a minimum of 5 k between the "+" and "-" pins to a nominal voltage level of 700 mVp-p. Both pins have DC bias of approximately 1.2 VDC. The AC signal is superimposed upon this analog ground voltage. These pins can be used single-ended, getting only half the voltage. Do NOT ground the unused pin. VCCA, VCCD (Voltage Inputs) To minimize noise, the analog and digital circuits in the ISD5008 device uses separate power busses. These +3 V busses lead to separate pins. Tie the VCCD pins together as close as possible and decouple both supplies as near to the package as possible. VSSA, VSSD (Ground Inputs) AUX OUT (Auxiliary Output) The ISD5008 series utilizes separate analog and digital ground busses. The analog ground (VSSA) pins should be tied together as close to the package as possible and connected through a lowimpedance path to power supply ground. The digital ground (VSSD) pin should be connected through a separate low-impedance path to power supply ground. These ground paths should be large enough to ensure that the impedance between the VSSA pins and the VSSD pin is less than 3 . The backside of the die is connected to VSSD through the substrate resistance. In a chip-onboard design, the die attach area must be connected to VSSD. The AUXOUT is an additional audio output pin, to be used, for example, to drive the speaker circuit in a "car kit." It drives a minimum load of 5 k and up to a maximum of 1 Vp-p. The AC signal is superimposed on approximately 1.2 VDC bias and must be capacitively coupled to the load. SP+, SP- (Speaker+/-) This is the speaker differential output circuit. It is designed to drive an 8 speaker connected across the speaker pins up to a maximum of 23.5 mW power. This stage has two selectable gains, 1.32 and 1.6, which can be chosen through the configuration registers. These pins are biased to approximately 1.2 VDC and, if used single-ended, must be capacitively coupled to their load. Do NOT ground the unused pin. ACAP (AGC Capacitor) This pin provides the capacitor connection for setting the parameters of the microphone AGC circuit. It should have a 4.7 F capacitor connected to ground. It cannot be left floating. This is because the capacitor is also used in the playback mode for the AutoMute circuit. This circuit reduces the amount of noise present in the output during quiet pauses. Tying this pin to ground gives maximum gain; to VCCA gives minimum gain for the AGC amplifier but will cancel the AutoMute function. 6 Voice Solutions in SiliconTM ISD5008 Product Figure 4: ISD5008 Series TSOP and PDIP/SOIC Pinouts ISD5008 ISD5008 28-PIN TSOP PDIP/SOIC 3 INTERNAL FUNCTIONAL BLOCKS Figure 5: Microphone Amplifier * 6 dB FTHRU Microphone MIC+ (300 mVp-p Max) AGC MIC- 1 (AGPD) AGC AGPD 0 1 Power Up Power Down To AutoMute ACAP (Playback Only) * Differential Path 15 VLS1 14 VLS0 13 VOL2 12 VOL1 11 VOL0 10 S1S1 9 S1S0 8 7 6 5 4 FLS0 3 FLD1 2 FLD0 1 FLPD 0 AGPD S1M1 S1M0 S2M1 S2M0 CFG1 ISD 7 ISD5008 Product Figure 6: AUX IN and ANA IN 1.0 / 1.414 / 2.0 / 2.828 Car Kit AUX IN AUX IN AMP 1 (AXPD) 2 (AXG1, AXG0) AXG1 0 0 1 1 AXG0 0 1 0 1 AUX IN AMP AXPD 0 1 Power Up Power Down Input Gain 1 1.414 2 2.828 0TLP Input Level .694 .491 .347 .245 .625 /.883 / 1.25 / 1.767 Chip Set ANA IN ANA IN AMP 1 (AIPD) 2 (AIG1,AIG0) AIG1 0 0 1 1 AIG0 0 1 0 1 ANA IN AMP AIPD 0 1 Power Up Power Down Input Gain 0.625 0.883 1.250 1.767 0TLP Input Level 1.11 .785 .555 .393 15 AIG1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AIG0 AIPD AXG1 AXG0 AXPD INS0 AOS2 AOS1 AOS0 AOPD OPS1 OPS0 OPA1 OPA0 VLPD CFG0 8 Voice Solutions in SiliconTM ISD5008 Product Figure 7: ISD5008 Core (Left Half) INPUT SOURCE MUX AGC AMP SUM1 SUMMING AMP 2 (S1M1,S1M0) SUM1 AUX IN AMP INSO 0 1 Source AGC AMP AUX IN AMP SUM1 MUX ANA IN AMP ARRAY FILTO S1S1 0 0 1 1 (INS0) S1M1 0 0 1 1 S1M0 0 1 0 1 SOURCE BOTH SUM1 MUX ONLY INP ONLY Power Down 2 (S1S1,S1S0) S1S0 0 1 0 1 SOURCE ANA IN AMP ARRAY FILTO N/C 15 AIG1 15 VLS1 14 AIG0 14 VLS0 13 AIPD 13 VOL2 12 11 10 9 INS0 9 8 7 6 5 4 3 2 1 0 AXG1 AXG0 AXPD 12 VOL1 11 VOL0 10 S1S1 AOS2 AOS1 AOS0 AOPD 8 7 6 5 OPS1 OPS0 4 FLS0 3 FLD1 OPA1 OPA0 VLPD 2 FLD0 1 FLPD 0 AGPD CFG0 CFG1 S1S0 S1M1 S1M0 S2M1 S2M0 ISD 9 ISD5008 Product Figure 8: ISD5008 Core (Right Half) FILTER MUX SUM1 LOW PASS FILTER ARRAY FLS0 0 1 Source SUM1 ARRAY FILTO SUM2 SUMMING AMP 2 (S2M1,S2M0) S2M1 0 0 1 1 SUM2 1 1 (FLS0) (FLPD) FLPD 0 1 Power Up Power Down S2M0 0 1 0 1 SOURCE BOTH ANA IN ONLY FILTO ONLY Power Down ANA IN AMP MULTILEVEL STORAGE ARRAY XCLK INTERNAL CLOCK 2 (FLD1,FLD0) FLD1 0 0 1 1 FLD0 0 1 0 1 SAMPLE RATE 8 kHz 6.4 kHz 5.3 kHz 4 kHz FILTER PASS BAND 3.4 kHz 2.7 kHz 2.3 kHz 1.7 kHz ARRAY 15 VLS1 14 VLS0 13 VOL2 12 VOL1 11 VOL0 10 S1S1 9 S1S0 8 7 6 5 4 FLS0 3 FLD1 2 FLD0 1 0 S1M1 S1M0 S2M1 S2M0 FLPD AGPD CFG1 10 Voice Solutions in SiliconTM ISD5008 Product Figure 9: Volume Control ANA IN AMP VOL MUX SUM2 SUM1 VOLUME CONTROL INP VOL 2 (VLS1,VLS0) 3 1 (VLPD) (VOL2,VOL1,VOL0) VLPD 0 1 Power Up Power Down VLS1 0 0 1 1 VLS0 0 1 0 1 SOURCE ANA IN AMP SUM2 SUM1 INP VOL2 0 0 0 0 1 1 1 1 11 10 9 INS0 9 S1S0 8 VOL1 0 0 1 1 0 0 1 1 7 VOL0 0 1 0 1 0 1 0 1 6 Attenuation 0 dB 4 dB 8 dB 12 dB 16 dB 20 dB 24 dB 28 dB 5 4 3 2 1 0 15 AIG1 15 VLS1 14 AIG0 14 VLS0 13 AIPD 13 12 AXG1 AXG0 AXPD 12 11 10 S1S1 AOS2 AOS1 AOS0 AOPD 8 7 6 5 OPS1 OPS0 4 FLS0 3 FLD1 OPA1 OPA0 VLPD 2 FLD0 1 FLPD 0 AGPD CFG0 CFG1 VOL2 VOL1 VOL0 S1M1 S1M0 S2M1 S2M0 ISD 11 ISD5008 Product Figure 10: Speaker and AUX OUT OUTPUT MUX VOL Car Kit AUX OUT (1 Vp-p Max) ANA IN AMP SP+ FILTO SP- 2 (OPA1, OPA0) 2 (OPS1,OPS0) OPA1 0 0 1 1 OPA0 0 1 0 1 SPKR Drive Power Down 3.6 Vp-p @ 150 23 mWatt @ 8 Power Down AUX OP Power Down Power Down Power Down 1 Vp-p Max @ 5k Speaker SUM2 OPS1 0 0 1 1 15 AIG1 14 AIG0 13 AIPD 12 11 10 AXPD 9 OPS0 0 1 0 1 8 SOURCE VOL ANA IN FILTO SUM2 7 6 5 4 3 2 1 0 AXG1 AXG0 INS0 AOS2 AOS1 AOS0 AOPD OPS1 OPS0 OPA1 OPA0 VLPD CFG0 Figure 11: ANA OUT Output ANA OUT MUX *FTHRU *INP *VOL ANA OUT+ *FILTO ANA OUT- *SUM1 *SUM2 1 (AOPD) 3 (AOS2,AOS1,AOS0) AOS2 0 0 0 0 1 1 1 1 AOS1 0 0 1 1 0 0 1 1 AOS0 0 1 0 1 0 1 0 1 FTHRU INP VOL FILTO SUM1 SUM2 N/C N/C AOPD 0 1 Power Up Power Down (1 Vp-p max. from AUX IN or ARRAY) (600 mVp-p max. from microphone input) Chip Set *DIFFERENTIAL PATH 15 AIG1 14 AIG0 13 AIPD 12 11 10 AXPD 9 INS0 8 7 6 5 4 3 2 1 0 AXG1 AXG0 AOS2 AOS1 AOS0 AOPD OPS1 OPS0 OPA1 OPA0 VLPD CFG0 12 Voice Solutions in SiliconTM ISD5008 Product 4 SERIAL PERIPHERAL INTERFACE (SPI) DESCRIPTION 7. As Interrupt data is shifted out of the ISD5008 MISO pin, control and address data is simultaneously being shifted into the MOSI pin. Care should be taken such that the data shifted in is compatible with current system operation. It is possible to read interrupt data and start a new operation within the same SPI cycle. 8. A record or playback operation begins with the RUN bit set and the operation ends with the RUN bit reset. 9. All operations begin with the rising edge of SS. The ISD5008 product operates from an SPI serial interface. The SPI interface operates with the following protocol. The data transfer protocol assumes that the microcontroller's SPI shift registers are clocked on the falling edge of the SCLK. With the ISD5008, data is clocked in on the MOSI pin on the rising clock edge. Data is clocked out on the MISO pin on the falling clock edge. 1. All serial data transfers begin with the falling edge of SS pin. 2. SS is held LOW during all serial communications and held HIGH between instructions. 3. Data is clocked in on the rising clock edge and data is clocked out on the falling clock edge. 4. Play and Record operations are initiated by enabling the device by asserting the SS pin LOW, shifting in an opcode and an address field to the ISD5008 device (refer to the Opcode Summary on the page 14). 5. The opcodes and address fields are as follows: <8 control bits> and <16 address bits>. 6. Each operation that ends in an EOM or Overflow will generate an interrupt, including the Message Cueing cycles. The Interrupt will be cleared the next time an SPI cycle is completed. 4.1 MESSAGE CUEING Message cueing allows the user to skip through messages, without knowing the actual physical location of the message. This operation is used during playback. In this mode, the messages are skipped 1600 times faster than in normal playback mode. It will stop when an EOM marker is reached. Then, the internal address counter will point to the next message. ISD 13 ISD5008 Product Table 6: Opcode Summary Instruction POWERUP LOADCFG0 LOADCFG1 SETPLAY PLAY SETREC REC MC (2) Opcode <8 bits>(1) Address <16 bits> 0110 0000 01X0 0010 Operational Summary Power-Up: See "Power-Up Sequence" Loads a 16-bit value into Configuration Register 0 Loads a 16-bit value into Configuration Register 1 Initiates Playback from address STOP STOPWRDN RINT 1. 2. 0111 0000 0101 0000 0111 0000 X = Don't Care. Changes in CFG0 are not recognized until CFG1 is loaded. The changes will occur at the rising edge of SS during the cycle that CFG1 is loaded. 4.2 POWER-UP SEQUENCE The ISD5008 will be ready for an operation after TPUD (25 ms approximately for 8 kHz sample rate). The user needs to wait TPUD before issuing an operational command. For example, to play from address 00 the following programing cycle should be used. The device will start playback at address 00 and it will generate an interrupt when an EOM is reached. It will then stop playback. Record Mode 1. Send POWERUP command. 2. Wait TPUD (power-up delay). Playback Mode 1. Send POWERUP command. 3. Load CFG0 and CFG1 for desired operation. 4. Send SETREC command with address 00. 2. Wait TPUD (power-up delay). 3. Load CFG0 and CFG1 for desired operation. 4. Send SETPLAY command with address 00. The device will start recording at address 00 and it will generate an interrupt when an overflow is reached (end of memory array) or when it has received a STOP command. It will then stop recording. 14 Voice Solutions in SiliconTM ISD5008 Product 4.3 SPI PORT The following diagram describes the SPI port and the control bits associated with it. Figure 12: SPI Port NOTE: Bytes 1 and 2 of the MOSI input may be address bits or configuration bits, depending on the selected mode in byte 3. 4.4 SPI CONTROL REGISTER The SPI control register provides control of individual device functions such as Play, Record, Message Cueing, Power-Up and Power-Down, Start and Stop operations, Ignore Address Pointers and Load Configuration Registers. Table 7: SPI Control Register Control Register RUN = = P/R = = 1 0 1 0 Bit Device Function Enable or Disable an operation Start Stop Selects Play or Record operation Play Record IAB = = 1 0 Control Register PU = = 1 0 Bit Device Function Master power control Power-Up Power-Down Ignore address control bit Ignore input address register (A15-A0) Use the input address register contents for an operation (A15-A0) Output of the row pointer register Input control and address register MC = = LC0 = = 1 0 1 0 Enable or Disable Message Cueing Enable Message Cueing Disable Message Cueing A15-A0 D15-D0 LC1 Load Configuration Reg 0 No Load = = 1 0 Load Configuration Reg 1 No Load ISD 15 AIG0 AIPD AXG1 AXG0 AXPD INS0 AOS2 AOS1 AOS0 AOPD OPS1 OPS0 OPA1 OPA0 VLPD VLS0 VOL2 VOL1 VOL0 S1S1 S1S0 S1M1 S1M0 S2M1 S2M0 FLSO FLD1 FLD0 FLPD AGPD Volume Control Power Down D1 Filter Power Down AGC AMP Power Down SPKR & AUX OUT Control (2 bits) D2 D2 SAMPLE RATE (& Filter) Set Up (2 bits) D3 OUPUT MUX Select (2 bits) D4 D4 D3 FILTER MUX Select D5 ANA OUT Power Down D5 SUM2 SUMMING AMP Control (2 bits) D6 D7 D6 ANA OUT MUX Select (3 bits) D7 SUM 1 SUMMING AMP Control (2 bits) D8 D9 D8 Configuration Register 0 Configuration Register 1 INPUT SOURCE MUX Select (1 bit) See details on following pages. D9 SUM 1 MUX Select (2 bits) D10 See details on following pages. D10 AUX IN Power Down D11 AUX IN AMP Gain SET (2 bits) D12 D12 D11 VOLUME CONTROL (3 bits) ANA IN Power Down D13 ISD5008 Product D14 D13 Table 8: ANA IN AMP Gain SET (2 bits) AIG1 D15 NOTE: Table 9: D14 VOLUME CONT. MUX Select (2 bits) VLS1 D15 NOTE: 16 Voice Solutions in SiliconTM CFG0 D0 D1 D0 CFG1 ISD5008 Product Detail of Configuration Register 0 Volume Control Power Bit SPEAKER and AUX OUT Control Bits Bit 0 (VLPD) Bits 2,1 (OPA1, OPA0) 0 = Power ON 1 = Power OFF 00 = Power down SPKR and AUX 01 = SPKR ON, HIGH GAIN, AUX Power down 10 = SPKR ON, LOW GAIN, AUX Power down 11 = SPKR Powered down, AUX ON 00 = Source is VOL CONTROL (VOL) 01 = Source is ANA IN Input (ANA IN AMP) 10 = Source is LOW PASS FILTER (FILT0) 11 = Source is SUM2 SUMMING AMP (SUM2) 0 = Power ON 1 = Power OFF 000 = Source is MICROPHONE AMP (FTHRU) 001 = Source is INPUT MUX (INP) 010 = Source is VOLUME CONTROL (VOL) 011 = Source is LOW PASS FILTER (FILT0) 100 = Source is SUM1 SUMMING AMP (SUM1) 101 = Source is SUM2 SUMMING AMP (SUM2) 110 = Unused 111 = Unused 0 = Source is Microphone AGC AMP (AGC) 1 = Source is AUX IN Input (AUX IN AMP) 0 = Power ON 1 = Power OFF 00 = Input Gain = 1, OTLP input Level = 0.694 01 = Input Gain = 1.414, OTLP input Level = 0.491 10 = Input Gain = 2, OTLP input Level = 0.347 11 = Input Gain = 2.828, OTLP input Level = 0.245 0 = Power ON 1 = Power OFF 00 = Input Gain = 0.625, OTLP input Level = 1.11 01 = Input Gain = 0.883, OTLP input Level = 0.7l85 10 = Input Gain = 1.250, OTLP input Level = 0.555 11 = Input Gain = 1.767, OTLP input Level = 0.393 OUTPUT MUX Control Bits Bits 4,3 (OPS1, OPS0) ANA OUT Power Bit ANA OUT MUX Control Bits Bit 5 (AOPD) Bits 8,7,6 (AOS2, AOS1, AOS0) INPUT SOURCE MUX Control Bit AUX IN AMP Power Bit AUX IN AMP Control Bits Bit 9 (INS0) Bit 10 (AXPD) Bits 12,11 (AXG1, AXG0) ANA IN AMP Power Bit ANA IN AMP Control Bits Bit 13 (AIPD) Bits 15,14 (AIG1, AIG0) ISD 17 ISD5008 Product Detail of Configuration Register 1 AGC Power Control Bit LOW PASS FILTER Power Control Bit SAMPLE RATE and LOW PASS FILTER Control Bits FILTER MUX Control bits SUM 2 SUMMING AMP Control Bits Bit 0 (AGPD) Bit 1 (FLPD) Bits 3,2 (FLD1, FLD0) 0 = Power ON 1 = Power OFF 0 = Power ON 1 = Power OFF 00 = Sample Rate = 8 KHz, FPB = 3.4 KHz 01 = Sample Rate = 6.4 KHz, FPB = 2.7 KHz 10 = Sample Rate = 5.3 KHz, FPB = 2.3 KHz 11 = Sample Rate = 4 KHz, FPB = 1.7 KHz 0 = Source is SUM1 SUMMING AMP (SUM1) 1 = Source is Analog Memory Array (ARRAY) 00 = Source is both ANA IN AMP and FILT0 01 = Source is ANA IN Input (ANA IN AMP) ONLY 10 = Source is LOW PASS FILTER (FILT0) ONLY 11 = Power Down SUM2 SUMMING AMP 00 = Source is both SUM1 and INP 01 = Source is SUM1 SUMMING AMP (SUM1) ONLY 10 = Source is INPUT MUX (INP) ONLY 11 = Power Down SUM1 SUMMING AMP 00 = Source is ANA IN Input (ANA IN AMP) 01 = Source is Analog Memory Array (ARRAY) 10 = Source is LOW PASS FILTER (FILT0) 11 = UNUSED 000 = Attenuation = 0 dB 001 = Attenuation = 4 dB 010 = Attenuation = 8 dB 011 = Attenuation = 12 dB 100 = Attenuation = 16 dB 101 = Attenuation = 20 dB 110 = Attenuation = 24 dB 111 = Attenuation = 28 dB 00 = Source is ANA IN Input (ANA IN AMP) 01 = Source is SUM2 SUMMING AMP (SUM2) 10 = Source is SUM1 SUMMING AMP (SUM1) 11 = Source is INPUT MUX (INP) Bit 4 (FLS0) Bits 6,5 (S2M1, S2M0) SUM1 SUMMING AMP Control Bits Bit 8,7 (S1M1, S1M0) SUM1MUX Control Bits Bit 10,9 (S1S1, S1S0) VOLUME CONTROL Control Bits Bits 13,12,11 (VOL2, VOL1, VOL0) VOL MUX Control Bits Bit 15,14 (VLS1, VLS0) Configuration Register Notes 1. Important: All changes to the internal settings of the ISD5008 are synchronized with the load of Configuration Register 1. A command to load Configuration Register 1 immediately transfers the input data to the internal settings of the device and the changes take place immediately at the end of the command when SS\ goes HIGH. A load to Configuration Register 0 sends the new data to a temporary register in the ISD5008 and does not affect the internal settings of the device. The next time Configuration Register 1 is loaded, data will also transfer from the temporary register to the Configuration 0 Register and effect the desired changes. See Figure Table 13. 2. Configuration Registers may be loaded with data at any time, including when the chip is powered down using the PU bit in the SPI Control Register. The PU bit in the SPI Control Word will have to be set to a "1" before the changes in configuration will be seen. 18 Voice Solutions in SiliconTM ISD5008 Product Figure 13: Configuration Register Programming Sequence Temporary Register Command = Load Configuration Register 0 Configuration Register 0 Configuration Register 1 } { Command = Load Configuration Register 1 MOSI Input Shift Register (16 bits) Control Word (C7-C0) Figure 14: SPI Interface Simplified Block Diagram Configuration Registers D15 CFG1 (1) D0 D15 CFG0 D15 - D0 D0 1. See Table 8 for bit details. ISD 19 ISD5008 Product Figure 15: Typical Digital Cellular Phone Integration ISD5008 MIC IN+ MIC IN- ANA OUT+ MIC+ ANA OUT- MIC- Microphone Earpiece RF Section IF Interface DSP SP OUT+ SP OUT - ANA IN SP+ SP- Voice Band Codec SPI AUX IN SPI AUX OUT Microcontroller Keypad Display EEPROM Flash Car Kit 20 Voice Solutions in SiliconTM ISD5008 Product 5 OPERATIONAL MODES DESCRIPTION 5.1 FEED THROUGH MODE This mode enables the ISD5008 to connect to a base band cell phone or cordless phone chip set without affecting the audio source or destination. There are two paths involved, the transmit path and the receive path. The transmit path connects the ISD chip's microphone source through to the microphone input on the base band chip set. The receive path connects the base band chip set's speaker output through to the speaker driver on the ISD chip. This allows the ISD chip to substitute for those functions and incidentally gain access to the audio to and from the base band chip set. Figure 15 shows one possible connection to such a chip set. Figure 16 shows the part of the ISD5008 block diagram that is used in Feed Through Mode. The rest of the chip will be powered down to conserve power. The bold lines highlight the audio paths. Note that the Microphone to ANA OUT +/- path is differential. The ISD5008 can operate in many different modes. It's flexibility allows the user to configure the chip such that almost any input can mixed with any other input and then be directed to any output. The variable settings for the ANA and AUX input amplifiers plus the microphone AGC and speaker volume controls make it possible to use the device with most existing cell phone or cordless phone chip sets with no external level adjustment. Several modes will be found in most applications, however. Please refer to the ISD5008 block diagram to better understand the following modes. In all cases, we are assuming that the chip has been powered up with the PU bit in the SPI control register and that a time period of TPUD has elapsed after that bit was set: Figure 16: Basic Feed-Thru Mode FTHRU 6 dB INP VOL Microphone MIC+ MIC- SUM2 1 (AOPD) 3 (AOS2,AOS1,AOS0) FILTO ANA OUT- SUM1 ANA OUT+ ANA OUT MUX Chip Set .625 /.883 / 1.25 / 1.767 VOL ANA IN AMP 1 (AIPD) SUM2 2 (AIG1,AIG0) ANA IN AMP FILTO OUTPUT MUX Speaker SP+ SP- 2 (OPA1, OPA0) Chip Set ANA IN 2 (OPS1,OPS0) ISD 21 ISD5008 Product To select this mode, the following control bits must be configured in the ISD5008 configuration registers. To set up the transmit path: 1. Select the FTHRU path through the ANA OUT MUX--Bits AOS0, AOS1 and AOS2 control the state of the ANAOUT MUX. These are the D6, D7 and D8 bits respectively of Configuration Register 0 (CFG0) and they should all be ZERO to select the FTHRU path. 2. Power up the ANA OUT amplifier--Bit AOPD controls the power up state of ANA OUT. This is bit D5 of CFG0 and it should be a ZERO to power up the amplifier. To set up the receive path: 1. Set up the ANA IN amplifier for the correct gain--Bits AIG0 and AIG1 control the gain settings of this amplifier. These are bits D14 and D15 respectively of CFG0. The input level at this pin determines the setting of this gain stage. Table 4 will help determine this setting. In this example we will assume that the peak signal never goes above 1 volt p-p single ended. That would enable us to use the 9dB attenuation setting, or where D14 is ONE and D15 is ZERO. 2. Power up the ANA IN amplifier--Bit AIPD controls the power up state of ANA IN. This is bit D13 of CFG0 and should be a ZERO to power up the amplifier. 3. Select the ANA IN path through the OUTPUT MUX--Bits OPS0 and OPS1 control the state of the OUTPUT MUX. These are bits D3 and D4 respectively of CFG0 and they should be set to the state where D3 is ONE and D4 is ZERO to select the ANA IN path. 4. Power up the Speaker Amplifier--Bits OPA0 and OPA1 control the state of the Speaker and AUX amplifiers. These are bits D1 and D2 respectively of CFG0. They should be set to the state where D1 is ONE and D2 is ZERO. This powers up the Speaker Amplifier and configures it for it's higher gain setting for use with a piezo speaker element and also powers down the AUX output stage. The status of the rest of the functions in the ISD5008 chip must be defined before the configuration registers settings are updated: 1. Power down the Volume Control Element--Bit VLPD controls the power up state of the Volume Control. This is bit D0 of CFG0 and it should be set to a ONE to power down this stage. 2. Power down the AUX IN amplifier--Bit AXPD controls the power up state of the AUX IN input amplifier. This is bit D10 of CFG0 and it should be set to a ONE to power down this stage. 3. Power down the SUM1 and SUM2 Mixer amplifiers--Bits S1M0 and S1M1 control the SUM1 mixer and bits S2M0 and S2M1 control the SUM2 mixer. These are bits D7 and D8 in CFG1 and bits D5 and D6 in CFG1 respectively. All 4 bits should be set to a ONE to power down these two amplifiers. 4. Power down the FILTER stage--Bit FLPD controls the power up state of the FILTER stage in the device. This is bit D1 in CFG1 and should be set to a ONE to power down the stage. 5. Power down the AGC amplifier--Bit AGPD controls the power up state of the AGC amplifier. This is bit D0 in CFG1 and should be set to a ONE to power down this stage. 6. Don't Care bits--The following stages are not used in Feed Through Mode. Their bits may be set to either level. In this example we will set all the following bits to a ZERO. (a). Bit INS0, bit D9 of CFG0 controls the Input Source Mux. (b). Bits AXG0 and AXG1 are bits D11 and D12 respectively in CFG0. They control the AUX IN amplifier gain setting. (c). Bits FLD0 and FLD1 are bits D2 and D3 respectively in CFG1. They control the sample rate and filter band pass setting. (d). Bit FLS0 is bit D4 in CFG1. It controls the FILTER MUX. (e). Bits S1S0 and S1S1 are bits 22 Voice Solutions in SiliconTM ISD5008 Product D9 and D10 of CFG1. They control the SUM1 MUX. (f). Bits VOL0, VOL1 and VOL2 are bits D11, D12 and D13 of CFG1. They control the setting of the Volume Control. (g). Bits VLS0 and VLS1 are bits D14 and D15 of CFG1. They control the Volume Control MUX. The end result of the above set up is CFG0=0100 0100 0000 1011 (hex 440B) and CFG1=0000 0001 1110 0011 (hex 01E3). Since both registers are being loaded, CFG0 is loaded followed by the loading of CFG1. These two registers must be loaded in this order. The internal set up for both registers will take effect synchronously with the rising edge of SS. amplifier. These are bits D7 and D8 respectively of CFG1 and they should be set to the state where D7 is ONE and D8 is ZERO to select the SUM1 MUX (only) path. 3. Select the SUM1 SUMMING amplifier path through the FILTER MUX--Bit FLS0 controls the state of the FILTER MUX. This is bit D4 of CFG1 and it must be set to ZERO to select the SUM1 SUMMING amplifier path. 4. Power up the LOWPASS FILTER--Bit FLPD controls the power up state of the LOWPASS FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS FILTER STAGE. 5. Select the 6.4 kHz sample rate--Bits FLD0 and FLD1 select the Low Pass filter setting and sample rate to be used during record and playback. These are bits D2 and D3 of CFG1. To enable the 6.4 kHz sample rate, D2 must be set to ONE and D3 set to ZERO. 6. Select the LOW PASS FILTER input (only) to the S2 SUMMING amplifier--Bits S2M0 and S2M1 control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6 respectively of CFG1 and they should be set to the state where D5 is ZERO and D6 is ONE to select the LOW PASS FILTER (only) path. In this mode, the elements of the original PASS THROUGH mode do not change. The sections of the chip not required to add the record path remain powered down. In fact, CFG0 does not change and remains CFG0=0100 0100 0000 1011 (hex 440B). CFG1 changes to CFG1=0000 0000 1100 0101 (hex 00C5). Since CFG0 is not changed, it is only necessary to load CFG1. Note that if only CFG0 was changed, it would be necessary to load both registers. 5.2 CALL RECORD The call record mode adds the ability to record the incoming phone call. In most applications, the ISD5008 would first be set up for Feed Through Mode as described above. When the user wishes to record the incoming call, the set up of the chip is modified to add that ability. For the purpose of this explanation, we will use the 6.4 kHz sample rate during recording. The block diagram of the ISD5008 shows that the Multilevel Storage array is always driven from the SUM2 SUMMING amplifier. The path traces back from there through the LOW PASS Filter, THE FILTER MUX, THE SUM1 SUMMING amplifier, the SUM1 MUX, then from the ANA in amplifier. Feed Through Mode has already powered up the ANA IN amp so we only need to power up and enable the path to the Multilevel Storage array from that point: 1. Select the ANA IN path through the SUM1 MUX--Bits S1S0 and S1S1 control the state of the SUM1 MUX. These are bits D9 and D10 respectively of CFG1 and they should be set to the state where both D9 and D10 are ZERO to select the ANA IN path. 2. Select the SUM1 MUX input (only) to the S1 SUMMING amplifier--Bits S1M0 and S1M1 control the state of the SUM1 SUMMING ISD 23 ISD5008 Product 5.3 MEMO RECORD The Memo Record mode sets the chip up to record from the local microphone into the chip's Multilevel Storage Array. A connected cellular telephone or cordless phone chip set may remain powered down and is not active in this mode. The path to be used is microphone input to AGC amplifier, then through the INPUT SOURCE MUX to the SUM1 SUMMING amplifier. From there the path goes through the FILTER MUX, the LOW PASS FILTER, the SUM2 SUMMING amplifier, then to the MULTILEVEL STORAGE ARRAY. In this instance, we will select the 5.3 kHz sample rate. The rest of the chip may be powered down. 1. Power up the AGC amplifier--Bit AGPD controls the power up state of the AGC amplifier. This is bit D0 of CFG1 and must be set to ZERO to power up this stage. 2. Select the AGC amplifier through the INPUT SOURCE MUX--Bit INS0 controls the state of the INPUT SOURCE MUX. This is bit D9 of CFG0 and must be set to a ZERO to select the AGC amplifier. 3. Select the INPUT SOURCE MUX (only) to the S1 SUMMING amplifier--Bits S1M0 and S1M1 control the state of the SUM1 SUMMING amplifier. These are bits D7 and D8 respectively of CFG1 and they should be set to the state where D7 is ZERO and D8 is ONE to select the INPUT SOURCE MUX (only) path. 4. Select the SUM1 SUMMING amplifier path through the FILTER MUX--Bit FLS0 controls the state of the FILTER MUX. This is bit D4 of CFG1 and it must be set to ZERO to select the SUM1 SUMMING amplifier path. 5. Power up the LOWPASS FILTER--Bit FLPD controls the power up state of the LOWPASS FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS FILTER STAGE. 6. Select the 5.3 kHz sample rate--Bits FLD0 and FLD1 select the Low Pass filter setting and sample rate to be used during record and playback. These are bits D2 and D3 of CFG1. To enable the 5.3 kHz sample rate, D2 must be set to ZERO and D3 set to ONE. 7. Select the LOW PASS FILTER input (only) to the S2 SUMMING amplifier--Bits S2M0 and S2M1 control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6 respectively of CFG1 and they should be set to the state where D5 is ZERO and D6 is ONE to select the LOW PASS FILTER (only) path. To set up the chip for Memo Record, the configuration registers are set up as follows: CFG0=0010 0100 0010 0001 (hex 2421). CFG1=0000 0001 0100 1000 (hex 0148). Only those portions necessary for this mode are powered up. 5.4 MEMO AND CALL PLAYBACK This mode sets the chip up for local playback of messages recorded earlier. The playback path is from the MULTILEVEL STORAGE ARRAY to the FILTER MUX, then to the LOW PASS FILTER stage. From there the audio path goes through the SUM2 SUMMING amplifier to the VOLUME MUX, through the VOLUME CONTROL then to the SPEAKER output stage. We will assume that we are driving a pizeo speaker element. This audio was previously recorded at 8 kHz. All unnecessary stages will be powered down. 1. Select the MULTILEVEL STORAGE ARRAY path through the FILTER MUX--Bit FLS0, the state of the FILTER MUX. This is bit D4 of CFG1 and must be set to ONE to select the MULTILEVEL STORAGE ARRAY. 2. Power up the LOWPASS FILTER--Bit FLPD controls the power up state of the LOWPASS FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS FILTER STAGE. 3. Select the 8.0 kHz sample rate--Bits FLD0 and FLD1 select the Low Pass filter setting and sample rate to be used during record 24 Voice Solutions in SiliconTM ISD5008 Product and playback. These are bits D2 and D3 of CFG1. To enable the 8.0 kHz sample rate, D2 and D3 must be set to ZERO. 4. Select the LOW PASS FILTER input (only) to the S2 SUMMING amplifier --Bits S2M0 and S2M1 control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6 respectively of CFG1 and they should be set to the state where D5 is ZERO and D6 is ONE to select the LOW PASS FILTER (only) path. 5. Select the SUM2 SUMMING amplifier path through the VOLUME MUX--Bits VLS0 and VLS1 control the state VOLUME MUX. These bits are bits D14 and D15, respectively of CFG1. They should be set to the state where D14 is ONE and D15 is ZERO to select the SUM2 SUMMING amplifier. 6. Power up the VOLUME CONTROL LEVEL-- Bit VLPD controls the power-up state of the VOLUME CONTROL attenuator. This is Bit D0 of CFG0. This bit must be set to a ZERO to power-up the VOLUME CONTROL. 7. Select a VOLUME CONTROL LEVEL--Bits VOL0, VOL1, and VOL2 control the state of the VOLUME CONTROL LEVEL. These are bits D11, D12, and D13, respectively, of CFG1. A binary count of 000 through 111 controls the amount of attenuation through that state. In most cases, the software will select an attenuation level according to the desires of the current users of the product. In this example, we will assume the user wants an attenuation of -12 dB. For that setting, D11 should be set to ONE, D12 should be set to ONE, and D13 should be set to a ZERO. 8. Select the VOLUME CONTROL path through the OUTPUT MUX--These are bits D3 and D4, respectively, of CFG0. They should be set to the state where D3 is ZERO and D4 is a ZERO to select the VOLUME CONTROL. 9. Power up the SPEAKER amplifier and select the HIGH GAIN mode--Bits OPA0 and OPA1 control the state of the speaker (SP+ and SP-) and AUX OUT outputs. These are bits D1 and D2 of CFG0. They must be set to the state where D1 is ONE and D2 is ZERO to power-up the speaker outputs in the HIGH GAIN mode and to power-down the AUX OUT. To set up the chip for Memo or Call Playback, the configuration registers are set up as follows: CFG0=0010 0100 0010 0010 (hex 2422). CFG1=0101 1001 1101 0001 (hex 59D1). Only those portions necessary for this mode are powered up. ISD 25 ISD5008 Product Table 10: Absolute Maximum Ratings (Packaged Parts)(1) Condition Junction temperature Storage temperature range Voltage applied to any pin Voltage applied to MOSI, SCLK, INT, RAC and SS pins (Input current limited to 20mA) Lead temperature (soldering - 10 seconds) V CC - VSS 1. Value 150C -65C to +150C (V SS - 0.3 V) to (VCC + 0.3 V) (V SS - 1.0 V) to 5.5V 300C -0.3 V to +7.0 V Stresses above those listed may cause permanent damage to the device. Exposure to the absolute maximum ratings may affect device reliability. Functional operation is not implied at these conditions. Table 11: Absolute Maximum Ratings (Die) (1) Condition Junction temperature Storage temperature range Voltage applied to MOSI, SCLK, INT, RAC and SS pins (Input current limited to 20mA) V CC - VSS 1. Value 150C -65C to +150C (V SS - 0.3 V) to 5.5V -0.3 V to +7.0 V Stresses above those listed may cause permanent damage to the device. Exposure to the absolute maximum ratings may affect device reliability. Functional operation is not implied at these conditions. Table 12: Operating Conditions (Packaged Parts) Condition Commercial operating temperature range (1) (1) Value 0C to +70C -20C to +70C -40C to +85C +2.7 V to +3.3 V 0V Extended operating temperature Industrial operating temperature (1) (2) Supply voltage (VC C) Ground voltage (V SS) (3) 1. 2. 3. Case Temperature V CC = V CCA = VC C D V SS = V SSA = VSSD Table 13: Operating Conditions (Die) Condition Commercial operating temperature range Supply voltage (VC C) (1) Ground voltage (V SS 1. 2. Value 0C to +50C +2.7 V to +3.3 V 0V ) (2) V CC = V CCA = VC C D V SS = V SSA = VSSD 26 Voice Solutions in SiliconTM ISD5008 Product Table 14: General Parameters Symbol VIL VIH VOL VOL1 Parameters Input Low Voltage Input High Voltage Output Low Voltage RAC, INT Output Low Voltage Output High Voltage VCC Current (Operating) -- Playback -- Record -- Feedthru VCC Current (Standby) Input Leakage Current MISO Tristate Current 1 VCC - 0.4 VCC x 0.8 0.4 0.4 Min(2) Typ(1) Max(2) VCC x 0.2 V V V V IOL = 10 A IOL = 1 mA Units Conditions VOH ICC V IOH = -10 A No load(3) No load (3) No load (3) (3) (4) 15 25 12 1 10 1 10 mA mA mA A A A ISB IIL IHZ 1. 2. 3. 4. Typical values: TA = 25C and Vcc = 3.0 V. All min/max limits are guaranteed by ISD via electrical testing or characterization. Not all specifications are 100 percent tested. VCCA and VCCD summed together. SS = VCCA = VCCD, XCLK = MOSI = VSSA= VSSD and all other pins floating. ISD 27 ISD5008 Product Table 15: Timing Parameters Symbol FS Characteristic Sampling Frequency Min(2) Typ(1) 8.0 6.4 5.3 4.0 Max(2) Units kHz kHz kHz kHz (5) (5) (5) (5) Conditions FCF Filter Pass Band 8.0 kHz (sample rate) 6.4 kHz (sample rate) 5.3 kHz (sample rate) 4.0 kHz (sample rate) Record Duration 8.0 kHz (sample rate) 6.4 kHz (sample rate) 5.3 kHz (sample rate) 4.0 kHz (sample rate) Playback Duration 8.0 kHz (sample rate) 6.4 kHz (sample rate) 5.3 kHz (sample rate) 4.0 kHz (sample rate) Power-Up Delay 8.0 kHz (sample rate) 6.4 kHz (sample rate) 5.3 kHz (sample rate) 4.0 kHz (sample rate) Stop or Pause Record or Play 8.0 kHz (sample rate) 6.4 kHz (sample rate) 5.3 kHz (sample rate) 4.0 kHz (sample rate) RAC Clock Period 8.0 kHz (sample rate) 6.4 kHz (sample rate) 5.3 kHz (sample rate) 4.0 kHz (sample rate) RAC Clock Low Time 8.0 kHz (sample rate) 6.4 kHz (sample rate) 5.3 kHz (sample rate) 4.0 kHz (sample rate) 3.4 2.7 2.3 1.7 kHz kHz kHz kHz 3-dB Roll-Off Point(3) (7) 3-dB Roll-Off Point(3) (7) 3-dB Roll-Off Point(3) (7) 3-dB Roll-Off Point(3) (7) TREC 4 5 6 8 min min min min (6) (6) (6) (6) TPLAY 4 5 6 8 min min min min (6) (6) (6) (6) TPUD 25 31.25 37.5 50 msec msec msec msec TSTOP OR PAUSE 50 62.5 75 100 msec msec msec msec (9) (9) (9) (9) TRAC 200 250 300 400 msec msec msec msec TRACLO 25 31.25 37.5 50 msec msec msec msec 28 Voice Solutions in SiliconTM ISD5008 Product Table 15: Timing Parameters Symbol TRACM Characteristic RAC Clock Period in Message Cueing Mode 8.0 kHz (sample rate) 6.4 kHz (sample rate) 5.3 kHz (sample rate) 4.0 kHz (sample rate) RAC Clock Low Time in Message Cueing Mode 8.0 kHz (sample rate) 6.4 kHz (sample rate) 5.3 kHz (sample rate) 4.0 kHz (sample rate) Total Harmonic Distortion ANA IN to ARRAY, ARRAY to SPKR Min(2) Typ(1) Max(2) Units Conditions 125 156.3 187.5 250 sec sec sec sec TRACML 15.63 19.53 23.44 31.25 sec sec sec sec THD 1 2 % @1 kHz at 0TLP, sample rate = 5.3kHz Table 16: Analog Parameters Symbol Characteristic (14) Min(2) Typ(1) Max(2) Units Conditions MICROPHONE INPUT VMIC+/- VMIC (0TLP) MIC +/- Input Voltage MIC +/- input reference transmission level point (0TLP) Gain from MIC+/- input to ANA OUT MIC +/- Gain Tracking Microphone input resistance Microphone AGC Amplifier Range 3 208 300 mV mV Peak-to-Peak (4)(8) Peak-to-Peak(4)(10) AMIC AMIC (GT) RMIC AAGC ANA IN (14) VANA IN VANA IN (0TLP) AANA IN (SP) 5.5 6.0 6.5 dB 1 kHz at VMIC (0TLP)(4) 0.1 5 10 15 dB k dB 1 kHz, +3 to -40 dB 0TLP Input MIC- and MIC+ pins 6 40 Over 3-300 mV Input Range ANA IN Input Voltage ANA IN (0TLP) Input Voltage Gain from ANA IN to SP+/- 1.11 1.6 V V Peak-to-Peak (6dB gain setting) Peak-to-Peak (6dB gain setting)(10) 4 Steps of 3 dB 6 to 15 dB ISD 29 ISD5008 Product Table 16: Analog Parameters Symbol Characteristic Min(2) Typ(1) -4 to +5 Max(2) Units dB Conditions 4 Steps of 3 dB AANA IN (AUX OUT) Gain from ANA IN to AUX OUT AANA IN (GA) AANA IN (GT) RANA IN AUX IN(14) VAUX IN VAUX IN (0TLP) AUX IN Input Voltage AUX IN (0TLP) Input Voltage ANA IN Gain Accuracy ANA IN Gain Tracking ANA IN Input Resistance -0.5 +0.5 0.1 60 to 102 dB dB k (11) 1000 Hz, +3 to -40 dB 0TLP Input, 6dB setting See Ra in Figure 2 1.0 694.2 V mV Peak-to-Peak (0 dB gain setting) Peak-to-Peak (0 dB gain setting)(10) 4 Steps of 3dB AAUX IN (ANA OUT) Gain from AUX IN to ANA OUT AAUX IN (GA) AAux IN (GT) RAux IN AUX IN Gain Accuracy AUX IN Gain Tracking AUX IN Input Resistance -0.5 0 to 9 dB +0.5 0.1 21 to 40 dB dB k (11) 1000 Hz, +3 to -40 dB 0TLP Input, 0dB setting See Ra in Figure 3 SPEAKER OUTPUTS(14) VSPHG RSPLG RSPHG CSP VSPAG SP+/- Output Voltage (High Gain setting) SP+/- Output Load Imp. (Low Gain) SP+/- Output Load Imp. (High Gain) SP+/- Output Load Cap. SP+/- Output Bias Voltage (analog ground) Speaker Output DC Offset -100 1.2 8 3.6 V Peak-to-Peak, differential load = 150; OPA1, OPA0 = 01 OPA1, OPA0 = 10 70 OPA1, OPA0 = 01 100 pF VDC VSPDCO 100 mVDC With ANA IN to Speaker, ANA IN AC coupled to VSSA Speaker load = 150 (12)(13) ICNANA IN/(SP+/-) ANA IN to SP+/- Idle Channel Noise CRT(SP+/-)/ANA OUT -65 dB SP+/- to ANA OUT Cross Talk -65 dB 1kHz 0TLP input to ANA IN, with MIC+/- and AUX IN AC coupled to VSSA, and measured at ANA OUT feedthrough mode (12) Measured with a 1kHz,100 mVpp sine wave input at VCCA and VCCD pins PSRR Power Supply Rejection Ratio -50 dB 30 Voice Solutions in SiliconTM ISD5008 Product Table 16: Analog Parameters Symbol FR POUTLG SINAD ANA OUT(14) SINAD SINAD MIC IN to ANA OUT +/SINAD AUX IN to ANA OUT (0 to 9 dB) Idle Channel Noise-- Microphone Idle Channel Noise-- AUX IN (0 to 9 dB) Power Supply Rejection Ratio ANA OUT+ and ANA OUT- ANA OUT+ to ANA OUT- Minimum Load Impedence Frequency Response (300-3400 Hz) -100 -50 62.5 dB Load = 5k (12)(13) Load = 5k (12)(13) Load = 5k (12)(13) Load = 5k (12)(13) Characteristic Frequency Response (300-3400 Hz) Power Output (Low Gain Setting) SINAD ANA IN to SP+/- Min(2) -0.25 Typ(1) Max(2) +0.25 Units dB Conditions With 0TLP input to ANA IN, 6dB setting (12) Differential load at 8 23.5 mW RMS dB 62.5 0TLP ANA IN input minimum gain, 150 load (12)(13) SINAD 62.5 dB ICNMIC/ANA OUT ICNAUX IN/ANA OUT -65 dB -65 dB PSRR(ANA OUT) dB Measured with a 1kHz, 100mVpp sine wave to VCCA, VCCD pins Inputs AC coupled to VSSA VBIAS VOFFSET RL FR 1.2 VDC +100 mVDC Inputs AC coupled to VSSA 5 k Differential Load -0.25 +0.25 dB 0TLP input to MIC+/- in feedthrough mode. 0TLP input to AUX IN in feedthrough mode(12) 1kHz 0TLP output from ANA OUT, with ANA IN AC coupled to VSSA, and measured at SP+/- (12) CRTANA OUT/(SP+/-) ANA OUT to SP+/Cross Talk -65 dB CRTANA OUT/AUX OUT ANA OUT to AUX OUT Cross Talk -65 dB 1kHz 0TLP output from ANA OUT, with ANA IN AC coupled to VSSA, and measured at AUX OUT(12) AUX OUT(14) VAUX OUT RL CL AUX OUT--Maximum Output Swing Minimum Load Impedence Maximum Load Capacitance 5 1.0 Vpp 5 k Load k 100 pF ISD 31 ISD5008 Product Table 16: Analog Parameters Symbol VBIAS SINAD Characteristic AUX OUT SINAD--ANA IN to AUX OUT Idle Channel Noise-- ANA IN to AUX OUT AUX OUT to ANA OUT cross Talk 62.5 Min(2) Typ(1) 1.2 Max(2) Units VDC dB 0TLP ANA IN input, minimum gain, 5k load (12)(13) Load = 5k (12)(13) Conditions ICN(AUX OUT) CRTAUX OUT/ANA OUT -65 dB -65 dB 1 kHz 0TLP input to ANA IN, with MIC +/- and AUX IN AC and coupled to VSSA, measured at SP+/-, load = 5k. Referenced to nominal 0TLP @ output VOLUME CONTROL (14) AOUT Output Gain Gain Accuracy -0.5 -28 to 0 0.5 dB dB 8 Steps of 4 dB, referenced to output ANA IN = 1 kHz 0TLP, 6dB Gain setting, measured differentially at SP+/- 1. 2. 3. 4. 5. Typical values: TA = 25C and Vcc = 3.0V. All min/max limits are guaranteed by ISD via electrical testing or characterization. Not all specifications are 100 percent tested. Low-frequency cut off depends upon the value of external capacitors (see Pin Descriptions). Differential input mode. Nominal differential input is 208 mVp-p. (0 dBm0) Sampling frequency can vary as much as -6/+4 percent over the industrial temperature and voltage ranges. For greater stability, an external clock can be utilized (see Pin Descriptions). Sampling frequency will be accurate within 1% for 5.3kHz, and 5% for 4.0, 6.4 and 8.0 kHz sampling rates at room temperature. Playback and Record Duration can vary as much as -6/+4 percent over the industrial temperature and voltage ranges. For greater stability, an external clock can be utilized (See Pin Descriptions). Playback and record durations are accurate within 1% for 5.3kHz, and 5% for 4.0, 6.4 and 8.0kHz sampling rates at room temperature. Filter specification applies to the low pass filter. Therefore, from input to output, expect a 6 dB drop by nature of passing through the filter twice. For optimal signal quality, this maximum limit is recommended. When a record command is sent, TRAC = TRAC + TRACLO on the first row addressed. 6. 7. 8. 9. 10. The maximum signal level at any input is defined as 3.17dB higher than the reference transmission level point. (0TLP) This is the point where signal clipping may begin. 11. Measured at 0TLP point for each gain setting. See Table 4 and Table 5. 12. 0TLP is the reference test level through inputs and outputs. See Table 4 and Table 5. 13. Referenced to 0TLP input at 1kHz, measured over 300 to 3,400 Hz bandwidth. 14. For die, only typical values from Analog Parameters are applicable. 32 Voice Solutions in SiliconTM ISD5008 Product Table 17: SPI AC Parameters(1) Symbol TSSS TSSH TDIS TDIH TPD TDF TSSmin TSCKhi TSCKlow F0 1. 2. Characteristics SS Setup Time SS Hold Time Data in Setup Time Data in Hold Time Output Delay Output Delay to hiZ SS HIGH SCLK High Time SCLK Low Time CLK Frequency Min 500 500 200 200 Max Units nsec nsec nsec nsec Conditions 500 500 1 400 400 1,000 nsec nsec sec nsec nsec kHz (2) Typical values: TA= 25C and Vcc= 3.0 V. Timing measured at 50 percent of the VCC level. Tristate test condition ISD 33 ISD5008 Product 6 TIMING DIAGRAMS Figure 17: SPI Timing Diagram Figure 18: 8-Bit SPI Command Format 34 Voice Solutions in SiliconTM ISD5008 Product Figure 19: 24-Bit SPI Command Format SS BYTE 1 SCLK BYTE 2 BYTE 3 MOSI D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 C0 C1 C2 C3 C4 C5 C6 C7 MISO OVF EOM A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 X X X X X X Figure 20: Playback/Record and Stop Cycle ISD 35 ISD5008 Product 7 DEVICE PHYSICAL DIMENSIONS Figure 21: 28-Lead 8x13.4 mm Plastic Thin Small Outline Package (TSOP) Type I (E) Table 18: Plastic Thin Small Outline Package (TSOP) Type I (E) Dimensions INCHES Min A B C D E F G H I J NOTE: MILLIMETERS Max 0.535 0.469 0.319 0.006 Min 13.20 11.70 7.90 0.05 0.17 0.22 0.55 0.041 6 0.028 0.008 0.95 0 0.50 0.10 1.00 3 0.55 1.05 6 0.70 0.21 Nom 13.40 11.80 8.00 Max 13.60 11.90 8.10 0.15 0.27 Nom 0.528 0.465 0.315 0.520 0.461 0.311 0.002 0.007 0.009 0.0217 0.011 0.037 0 0.020 0.004 0.039 3 0.022 Lead coplanarity to be within 0.004 inches. 36 Voice Solutions in SiliconTM ISD5008 Product Figure 22: 28-Lead 0.600-Inch Plastic Dual Inline Package (PDIP) (P) Table 19: Plastic Dual Inline Package (PDIP) (P) Dimensions INCHES Min A B1 B2 C1 C2 D D1 E F G H J S MILLIMETERS Max 1.455 Min 36.70 Nom 36.83 3.81 0.075 0.625 1.65 15.24 13.46 13.72 1.78 1.91 15.88 13.97 4.83 0.38 0.135 3.18 0.38 1.40 0.46 1.52 2.54 0.012 0.080 15 0.20 1.78 0 0.25 1.91 0.30 2.03 15 3.43 0.56 1.65 Max 36.96 Nom 1.450 0.150 1.445 0.065 0.600 0.530 0.070 0.540 0.550 0.19 0.015 0.125 0.015 0.055 0.018 0.060 0.100 0.008 0.070 0 0.010 0.075 0.022 0.065 ISD 37 ISD5008 Product Figure 23: 28-Lead 0.300-Inch Plastic Small Outline Integrated Circuit (SOIC) (S) Table 20: Plastic Small Outline Integrated Circuit (SOIC) (S) Dimensions INCHES Min A B C D E F G H NOTE: MILLIMETERS Max 0.711 0.104 0.299 0.0115 0.019 Min 17.81 2.46 7.42 0.127 0.35 Nom 17.93 2.56 7.52 0.22 0.41 1.27 0.410 0.040 10.16 0.61 10.31 0.81 10.41 1.02 Max 18.06 2.64 7.59 0.29 0.48 Nom 0.706 0.101 0.296 0.009 0.016 0.050 0.701 0.097 0.292 0.005 0.014 0.400 0.024 0.406 0.032 Lead coplanarity to be within 0.004 inches. 38 Voice Solutions in SiliconTM ISD5008 Product Figure 24: ISD5008 Series Bonding Physical Layout(1) (Unpackaged Die) MOSI MISO V SSD V SSD SS SCLK V CCD V CCD XCLK INT RAC V SSA ISD5008 Series I. Die Dimensions X: 166.5 1 mils Y: 302.4 1 mils Die Thickness (3) 11.5 1.0 mils Pad Opening (min) 90 x 90 microns 3.5 x 3.5 mils ISD5008 II. III. V SSA AUXOUT MIC+ MIC- ANAOUT+ ANAOUT- ACAP 1. 2. 3. AUX IN ANA IN SP- V SSA(2) SP+ V CCA (2) The backside of die is internally connected to V SS. It MUST NOT be connected to any other potential or damage may occur. Double bond recommended. This figure reflects the current die thickness. Please contact ISD as this thickness may change in the future. ISD 39 ISD5008 Product Table 21: ISD5008 Series Device Pin/Pad Designations, with Respect to Die Center (m) Pin VSSD VSSD MISO MOSI SS SCLK VCCD VCCD XCLK INT RAC VSSA VSSA MIC+ MIC- ANA OUT+ ANA OUT - ACAP SP- VSSA(1) SP+ VCCA(1) ANA IN AUX IN AUX OUT 1. Pin Name VSS Digital Power Supply VSS Digital Power Supply Master In Slave Out Master Out Slave In Slave Select Slave Clock VCC Digital Power Supply VCC Digital Power Supply External Clock Input Interrupt Row Address Clock VSS Analog Power Supply VSS Analog Power Supply Noninverting Microphone Input Inverting Microphone Input Noninverting Analog Output Inverting Analog Output AGC/AutoMute Cap Inverting Speaker Output VSS Analog Power Supply Noninverting Speaker Output VCC Analog Power Supply Analog Input Auxiliary Input Auxiliary Output X Axis -1837.0 -1665.4 -1325.7 -1063.8 -198.2 -14.8 169.4 384.8 564.7 794.7 1483.7 1885.1 -1943.2 -1735.4 -1502.9 --1251.2 -917.0 -632.6 -138.4 240.2 618.8 997.4 1249.9 1515.5 1758.4 Y Axis 3623.7 3623.7 3623.7 3623.7 3623.7 3623.7 3623.7 3623.7 3623.7 3623.7 3623.7 3623.7 -3615.9 -3615.9 -3615.9 -3615.9 -3615.9 -3615.9 -3615.9 -3615.9 -3615.9 -3615.9 -3615.9 -3615.9 -3615.9 Double bond recommended. 40 Voice Solutions in SiliconTM ISD5008 Product Figure 25: SD5008 Chip Scale Package (CSP) (Z) C F G A1 Ball Corner H A5 B5 D A4 B4 A3 B3 A2 A1 B2 B1 C5 C4 C3 C2 C1 I D5 D4 E5 E4 D3 D2 D1 e E3 E2 E1 e TOP VIEW A A1 A2 BOTTOM VIEW PIN Name MICACAP Ball Location A1 A2 A3 A4 A5 B1 B2 B3 B4 B5 C1 C2 C3 C4 C5 D1 D2 D3 D4 b SIDE VIEW VSSA VCCA AUX IN Table 22: Symbol A A1 A2 b C D e F G H I CSP Dimensions (mm) Min. -- 0.18 -- 0.30 -- -- Nom. -- -- 0.55 0.35 4.68 8.13 0.75 Max. 0.86 -- -- 0.40 -- -- MIC+ ANA OUTSPANA IN AUX OUT VSSA ANA OUT+ SP+ VCCD VSSA VSSD MISO SS XCLK -- -- -- -- 3.00 0.84 2.57 3.00 -- -- RAC VSSD MOSI D5 E1 E2 E3 E4 E5 -- -- SCLK VCCD INT ISD 41 ISD5008 Product 8 ORDERING INFORMATION ISD Part Number Description ISD5008-_ _ Product Family ISD5008 Product (4 to 8 minute durations) Special Temperature Field: Blank = Commercial Packaged (0C to +70C) or D I = = Commercial Die (0C to +50C) Extended (-20C to +70C) Industrial (-40C to +85C) Package Type: E= 28-Lead 8x13.4mm Plastic Thin Small Outline Package (TSOP) Type 1 P S X Z = = = = 28-Lead 0.600-Inch Plastic Dual Inline Package (PDIP) 28-Lead 0.300-Inch Plastic Small Outline Package (SOIC) Die Chip Scale Package (CSP) When ordering ISD5008 series devices, please refer to the following valid part numbers. Part Number ISD5008E ISD5008ED ISD5008EI ISD5008P ISD5008S ISD5008SD ISD5008SI ISD5008X ISD5008Z ISD5008ZD ISD5008ZI For the latest product information, access ISD's worldwide website at http://www.isd.com. 42 Voice Solutions in SiliconTM ISD5008 Product ISD 43 IMPORTANT NOTICES The warranty for each product of ISD (Information Storage Devices, Inc.), is contained in a written warranty which governs sale and use of such product. Such warranty is contained in the printed terms and conditions under which such product is sold, or in a separate written warranty supplied with the product. Please refer to such written warranty with respect to its applicability to certain applications of such product. These Products may be subject to restrictions on use. Please contact ISD for a list of the current additional restrictions on these Products. By purchasing these Products, the purchaser of these Products agrees to comply with such use restrictions. Please contact ISD for clarification of any restrictions described herein. ISD, reserves the right, without further notice, to change the ISD ChipCorder product specifications and/or information in this document and to improve reliability, functions and design. ISD assumes no responsibility or liability for any use of the ISD ChipCorder Product. ISD conveys no license or title, either expressed or implied, under any patent, copyright, or mask work right to the ISD ChipCorder Product, and ISD makes no warranties or representations that the ISD ChipCorder Product are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application examples and alternative uses of any integrated circuit contained in this publication are for illustration purposes only and ISD makes no representation or warranty that such applications shall be suitable for the use specified. The 100-year retention and 100K record cycle projections are based upon accelerated reliability tests, as published in the ISD Reliability Report, and are neither warranted nor guaranteed by ISD. Information contained in this ISD ChipCorder data sheet supersedes all data for the ISD ChipCorder Product published by ISD prior to October, 1999. This data sheet and any future addendum to this data sheet is (are) the complete and controlling ISD ChipCorder product specifications. In the event any inconsistencies exist between the information in this and other product documentation, or in the event that other product documentation contains information in addition to the information in this, the information contained herein supersedes and governs such other information in its entirety. Copyright(c) 1999, ISD (Information Storage Devices, Inc.) All rights reserved. ISD is a registered trademark of ISD. ChipCorder is a trademark of ISD. All other trademarks are properties of their respective owners. 2727 North First Street San Jose, California 95134 Tel: 408/943-6666 Fax: 408/544-1787 http://www.isd.com Part No. ISD5008PDS1-799 |
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